Designing CMOS folded-cascade operational amplifier And Implementation with CMOS Technology in IC

In this paper a new high gain bandwidth (GBW) and low power folded cascade OPAMP is presented. It has been implemented and layouted by CADENCE software in 0.18μm. Its DC gain is 82db and its bandwidth is 200MHz. Power consumption is one of the main design challenges in very-lowvoltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in lowvoltage fast settling operational amplifiers for switchedcapacitor applications are discussed. These techniques include a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V low-power operational amplifier merging these techniques are addressed. Simulation results of the circuit in a 0.025-mm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers. finally, the op-amp has been put in integrator of a first order sigma-delta modulator analog to digital convertor(ADC) and has been tested. Its result proof our idea and modified OP-AMP improve 10 DB output SNR of sigma-delta modulator rather than older OP-AMP.